Generally, in order to lower the resistance of a polysilicon gate electrode to accommodate a decrease in a critical dimension in CMOS device fabrication, a silicide layer is formed on the gate electrode. Since silicidation or salicidation is an optional process, a non-silicide or non-salicide area having no silicide may be formed on a specific portion of a device that requires higher resistance then the gate electrode.
A prior art method of forming a non-salicide area includes: forming a gate and spacers on a semiconductor substrate, forming an oxide layer thereon, forming a photoresist pattern covering an area that is not to be covered with salicide, removing the portions of the oxide layer which are not covered by the photoresist pattern, and forming a Ti- or Co-silicide layer on the uncovered areas. Thus, the non-salicide area is formed by preventing the silicide layer from being formed on the area covered by the photoresist pattern. The oxide layer is etched by wet etching, plasma dry etching (e.g., anisotropic etching), or by wet and dry etching using the photoresist pattern as an etch mask.
However, in the prior art method, if the oxide layer is wet etched, the etchant solution undercuts beneath the spacers. If, on the other hand, dry etching is performed, plasma damage occurs. Consequently, gate leakage is generated or the threshold voltage of the fabricated transistor is changed.
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